I assume #13191 make this less hard, although benefits may be small. Brief chat on IRC:
Me
While trying to get bitcoind to run on one the many *-pi’s out there, I wondered: has anyone ever tried to design a system on chip that’s optimal for this? @laanwj: provoostenator: you mean secp256k1 specific instructions? people have been thingking about it, could be done on a FPGA, but I don’t think it’s ever been done
Me:
echeveria seems to believe sha256 is the bottleneck (see #bitcoin), but also that anything outside the CPU would be too slow I/O to be worh it.
echeveria:
I looked at the Zynq combination FPGA / ARM devices a long time ago and came to the conclusion that the copy time even on the shared memory bus between the two chips would make it non viable. I’d enjoy being proved wrong though.
laanwj:
provoostenator: well sha256 extension instructions exist for ARM (supported on newer SoCs), I intend to add support for them at some point. But I would be surprised if that is the biggest bottleneck in validation.
echeveria:
yes, if there is high-bandwidth communication between two chpis that tends to dominate. I was > thinking of, say, RiscV extensions for secp256k1 validation so it’s in-core. for ARM it’s somewhat unlikely at this time
I have (at least) three devices to test this on, which all have 4 to 8 ARM Cortex-A53 cores, and 1- 4 GB RAM: an Android Xiaomi A1 (ABCore syncs the whole chain in less than a month), a NanoPi Neo Plus and a Khadas VIM2 Max.
Maybe this c++ code is useful: https://github.com/randombit/botan/issues/841