Constant-time operations on x86 and ARM #1138

"Intel and ARM recently published documentation that says that no instructions are guaranteed to be constant-time with respect to their data operands, unless a "data independent timing" flag in the IA32_UARCH_MISC_CTL register (Intel) or DIT register (arm64) is set.

(quote from https://lkml.org/lkml/2022/8/25/1372)

I haven't had a deep look so far. We probably report this also to Core.

See also https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html

Looks like on Intel, assuming that MSR is userspace-reachable, we can just set that and move on. If not, we need a kernel API which doesn't exist yet.